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POST Error Codes and Messages: Dell PowerEdge 7250 Systems Product Guide

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POST Error Codes and Messages

Dell™ PowerEdge™ 7250 Systems Product Guide

  POST Code Module Numbers

  Specific POST Code Modules

  Recovery Port 80 Codes

  Error Codes – Video Display

  Beep Codes

  Recovery Beep Codes


Table A-1 lists POST codes issued by SAL to I/O Port 0x80/0x81 during boot. The POST codes are listed in the order of occurrence.

NOTE: Some POST codes are not displayed because of timing and interaction delays with the BMC.

The following rules apply to the POST code encoding:

  • Bit 15: 1 – IA64 code being executed, 0 – IA32 code being executed

  • Bit 14: 1 – system stopped due to known failure, 0 – progress indication

  • All other module bits remain unmodified

  • Bit 13: 1 – fault or trap (no change in module numbers), 0 – normal execution

In case of fault or trap, only bit 13 is set and other bits are left unmodified. This allows detection of which module produced the fault.

  • Bit 12: Reserved

  • Bit 11-4: Module type

  • Bit 3-0: Sub module type

The module number identifies the major module such as Memory, PCI, ACPI and so forth. The submodule identifies the subfunction such as SPD read in progress, ECC error, or DIMM mismatch for memory module.

Module names and numbers are listed in the following tables.


POST Code Module Numbers

Table A-1. General IA64 POST Code Module Numbers

Code Value
(bit 8 = 1, bits 11:4 shown below)

Code Value
(bit 8 = 1, bits 11:4 shown below)


Display

0xFF

Reserved

North

0xFE

Reset condition

North

0xFD

Node BSP selection

North

0xFC

Early node init (SNCPEIM)

North

0xFB

Processor health/setup (CVDR PEIM

North

0xFA

PAL/FW health status

North

0xF9-F7

Memory initialization

North

Sub Modules Bits

Memory Initialization

 

15:12

11:8

7:4

3:0

 

North

8

F

7

0

Pass1 Entry

8

F

7

1

RAC initialization (Mem_DoRacInitialization())

8

F

7

2

Validate DIMMs (Mem_ValidateInstalledConfiguration())

8

F

7

3

Program MIRs/MITs (Mem_DoMirMitProgram())

8

F

7

4

Calculate CAS (Mem_CalcSysCas())

C

F

7

4

Calculate CAS Error Loop

8

F

7

5

Program CAS (Mem_SetMrhdCasLatency())

8

F

7

6

Set Mrhd DIMM Geometry (Mem_SetMrhdDimmGeometry())

8

F

7

7

Perform SLEW rate calibration (Mem_DoSlewRateCalibration)

8

F

7

8

Mem_InitDimmAndSetCasLatencyAndBurst()

8

F

7

9

DDR delay Calibration (Mem_DoDdrDelayCalibration())

8

F

8

0

DIMM path latency Calibration

8

F

8

1

DIMM Strobe Delay Calibration

8

F

8

2

Configure SNC timing

8

F

8

3

Set timings for write pattern

8

F

9

0

Levelization

8

F

9

8

Reconfigure memory

C

F

9

F

Levelization failed. No Memory Found

0xF6

Memory Test

North

0xF5

Platform Discovery

North

0xF4-F3

SBSP selection & Platform Init

North

0xF2

Memory Autoscan (stackless)

North

15:12

11:8

7:4

3:0

 

North

8

F

2

0

Pass1 Entry

8

F

2

1

Process Auto Scan Input

8

F

2

2

Execute Auto scan (C- code)

8

F

2

3

Process Auto Scan Output

0xF1

Recovery stackless

North

0xF0

Reserved

North

0xEF-0xEE

Memory Autoscan C-code

North

0xED-E8

Recovery C-Code

North

0xE8-0xE6

HOB

North

0xE5-0xC1

Reserved

North

0xC0

SALA to SALB/DXE handoff

North

0xB0-0xBF

Reserved

North

0xAF-80

Reserved for SAL MCA, INIT, PMI

North

0x7F to 0x60

SAL-B codes
SAL-B
SAL_C
SAL_F


South
South
South

0x60

SAL to EFI handoff

South

0x5F to 0x50

EFI

South

0x4F to 0x40

ACPI

South


Specific POST Code Modules

SAL-A Module

Table A-2. SAL-A POST Codes (BSP Only)

Code Number

Meaning

Display

0x8FE0

Reset Condition

North

0x8FD0

Node BSP selection

North

0x8FC0

Early node init (SNCPEIM)

North

0x8FB0

Processor health/setup (CVDR PEIM)

North

0x8FA0

PAL/FW health status

North

0x8F70

Memory Initialization Entry

North

0x8F71

RAC Initialization (Mem_DoRacInitialization())

North

0x8F72

Validate DIMMs (Mem_ValidateInstalledConfiguration())

North

0x8F73

Program MIRs/MITs (Mem_DoMirMitProgram())

North

0x8F74

Calculate CAS (Mem_CalcSysCas())

North

0xCF74

Calculate CAS Error Loop

North

0x8F75

Program CAS (Mem_SetMrhdCasLatency())

North

0x8F76

Set Mrhd DIMM Geomentry (Mem_SetMrhdDimmGeometry())

North

0x8F77

Perform SLEW rate calibration (Mem_DoSlewRateCalibration)

North

0x8F78

Mem_InitDimmAndSetCasLatencyAndBurst()

North

0x8F79

DDR delay Calibration (Mem_DoDdrDelayCalibration())

North

0x8F80

DIMM path latency Calibration

North

0x8F81

DIMM Strobe Delay Calibration

North

0x8F82

Configure SNC timing

North

0x8F83

Set timings for write pattern

North

0x8F90

Levelization

North

0x8F98

Reconfigure memory

North

0xCF9F

Levelization failed. No Memory Found

North

0x8F60

Memory Test

North

0x8F50

Platform Discovery

North

0x8F40

SBSP selection; ICHx device detection

North

0xCF40

ICHx device not found

North

0x8F50

Platform Init

North

0x8F20

Memory Autoscan entry

North

0x8F21

Process Auto Scan Input

North

0x8F22

Process Auto Scan Output

North

0x8F10

Recovery code entry

North

0x8EC0

Recovery Process Started

South

0x8EC1

Searching for Recovery Media

South

0x8EC2

Loading Recovery File

South

0x8EC3

Validating Recovery File

South

0x8EC4

Unlocking Flash Devices

South

0x8EC5

Erasing Flash Contents

South

0x8EC6

Programming Flash Contents

South

0x8EC7

Validating Flash Contents

South

0x8EC8

Recovery Process Complete

South

0xCEC1

Recovery Reading error(display toggles)

South

0xCECx

Recovery programming error (display toggels)

South

0x8E80

PEIM Handoff block entry

North

0x8C00

SALA to SALB/DXE handoff

North

0x8AF0
to
0x8800

Reserved for MCA, INIT, PMI

North

SAL-B Module

Table A-3. SAL-B POST Codes

Code Number

BSP, APs, Both

Meaning

Display

0x87FF

BSP+APs

First check point. Initialize cr.iva/ar.eflag/ar.cflg/cr.lrr0/cr.lrr1/cr.ifa/cr.itir

South

0x87FE

BSP onlyAndBSP+APs

Initialize io_base address, CPU#, health, etc. for CPU's Initialize min_state_area for all CPU's (cpu_data_base+cpu_bspstore_base+cpu_health) cpu_data_base points to min state save area. TOM below and above 4G

Allocate sal_mp_info_table data and sal_efi stack area and legacy_stack (temp)

Initialize legacy stack top and bottom for temporary use during POST only. INT_15,(FN# F788 in EM code) uses INT-8 timer tick for frequency calculation. (BSP+APs) Save ID, EID, Initialize BSPSTORE,SP

South

0x87FD

BSP only

Search FIT for legacy BIOS

South

0x07FD

BSP only

Then hang, if not found

If found copy top 64K legacy boot block ROM at xxxx:0000

South

0x87FC

BSP only

Search for legacy_nvm module (sal_legacy_nvm_module_1d)

South

0x07FC

BSP only

Then hang, if not found

Else continue by saving in RAM

South

0x87FB

BSP only

Search for efi_nvm module (sal_efi_nvm_module_1e)

South

0x07FB

BSP only

Then hang, if not found
Else continue by saving in RAM

Reserve 128k memory for NVM emulation

South

0x87FA

BSP only

Search for acpi_dsdt module (sal_acpi_data_module_16)

Ask for Address, size, type

South

0x07FA

BSP only

Then hang, if not found

Else continue by saving in RAM

South

0x87F9

BSP only

Search for addition information acpi_dsdt module

Ask for size, align, and scratch buff size

South

0x07F9

BSP only

Then hang, if not found

Else continue by saving in RAM

South

0x87F8

BSP only

Search for addition information acpi_dsdt module

Initialize scratch buffer

South

0x07F8

BSP only

Then hang, if not found

Else continue by saving in RAM

South

0x87F7

BSP only

Reserve ACPI_64 and ACPI_32 data area

Reserve MP table data area

Save SAL database & size

SAL shadow top (PELoader + SAL_F)

South

0x87F6

BSP only

Cache flush after PELoader shadow

South

0x07F6

BSP only

Hang, on ERROR

South

0x87F5

BSP only

Search for information on SAL_F module (sal_f_module_12)

By size, align, and scratch buff size

South

0x07F5

BSP only

Then hang, if not found or Information ERROR

SAL shadow bottom (PELoader + SAL_F)

Find SAL_F page size

Align to next 32K boundary and save address and size

South

0x87F4

BSP only

Search for addition information SAL_F module

Initialize scratch buffer

South

0x07F4

BSP only

Then hang, if not found

Else continue by saving in RAM

South

0x87F3

BSP only

Cache flush after SAL shadowed

South

0x07F3

BSP only

Hang on ERROR

South

0x87F5

BSP only

Search for information on SAL_F module (sal_f_module_12)

By size, align, and scratch buff size

South

0x07F5

BSP only

Then hang, if not found or Information ERROR

SAL shadow bottom (PELoader + SAL_F)

Find SAL_F page size

Align to next 32K boundary and save address and size

South

0x87F4

BSP only

Search for addition information SAL_F module

Initialize scratch buffer

South

0x07F4

BSP only

Then hang, if not found

Else continue by saving in RAM

South

0x87F3

BSP only

Cache flush after SAL shadowed

South

0x07F3

BSP only

Hang on ERROR

South

*0x87F2

BSP only

Initialize sal data top address

Physical equals to virtual for runtime use and above 4G

Load callbacks for byte/word checkpoint display entry and Address

SAL PMI address

EFI to SAL call back address

SAL procedure address SAL

SST base and address

SAL procedure entry base inside SST

Buildtime address where SAL_PROC entry is stored

Buildtime GP Runtime GP

SAL SST size

South

0x87F1

BSP only

Load PAL module

South

0x87F0

BSP+APs

BSP Shadow PAL module, initialize PAL shadow base, size, proc ptr initialize PAL procedure address entry & checksum AP's PAL PMI base will be set

South

0x07F0

BSP+APs

Hang on ERROR

South

0x87EF

BSP only

Cache flush after PAL shadow

South

0x07EF

BSP only

Hang on ERROR

South

0x87EE

BSP only

Find PAL shadow size + align through SAL call

South

0x07EE

BSP only

Hang on ERROR

South

0x87ED

BSP only

Find # of CPU's present in the system, # of CPU, # of IOAPIC

South

0x07ED

BSP only

Hang on ERROR

South

0x87EC

BSP only

Search for addition information EFI module (sal_efi_module_15) size, align, and scratch buff size. Initialize scratch buffer

South

0x07EC

BSP only

Hang if ERROR

South

0x87EB

BSP only

Save maximum (PAL,EFI) shadow size and alignment. Save PAL(ia32)/EFI shadow top address, size, alignment. EFI module shadow base address (virtual/Physical), size, bottom address (DATA+SAL+PAL+EFI). Update virtual address entries in translation register descriptor, addresses in MDT

South

0x87EA

BSP+APs

Cache flush shadow

South

0x07EA

BSP + APs

Hang on ERROR

South

0x87E9

BSP + APs

PAL call for memory Test for SELF TEST
(pal_mem_for_test_25)

South

0x07E9

BSP + APs

Hang, if Memory ERROR

South

0x87E8

BSP + APs

PAL call for PAL test (pal_test_proc_102) and save results

South

0x07E8

BSP + APs

Hang, if late self test. NOTE: This can be skipped by a build switch

South

0x87E7

BSP + APs

PAL Call for pal_bus_get_features function # (pal_bus_get_features_09)

South

0x07E7

BSP + APs

Hang if ERROR

South

0x87E6

BSP + APs

Set buslock mask=1 (non-atomic)

By PAL Call PAL Bus Set Feature (pal_bus_set_features_0a)

South

0x07E6

BSP + APs

Hang if ERROR

South

0x87E5

BSP + APs

Set PMI entry pointPAL Call (pal_pmi_entrypoint_20)

South

0x07E5

BSP + APs

Hang if ERROR

South

0x87E4

BSP + APs

PAL Cache Summary by PAL Call (pal_cache_summary_04)

South

0x07E4

BSP + APs

Hang if ERROR

South

0x87E3

BSP + APs

PAL Cache Information set. PAL Call cache_info_02

South

0x07E3

BSP + APs

Hang, if ERROR

South

0x87E2

BSP + APs

pal_mc_register_mem_1b/find CPU min state pointer

Should be able now to initialize health, bsp/ap, cache size line size, sapic ver, and cpuid
Set minimal state save area, BSPSTORE and SP

South

0x87E1

BSP + APs

Cache flush shadow

South

0x07E1

BSP + APs

Hang if ERROR

South

0x87E0

BSP + APs

Program IVA,ITR(0) for PAL,SAL runtime code & data area cr.iva/cr.ifa/cr.itir/itr[r0]

South

0x87DF

BSP + APs

Clear semaphore and wait for all CPUs to synchronize

South

0x87DE

BSP + APs

Sort CPU health. Already sorted for 2nd level BSP selection. Store BSP/AP flag for respective CPU

South

0x87DD

APs

Setup for interrupt wakeup re-initialization of BSPSTORE and SP if needed. Wait for interrupt wakeup

South

0x87DC

BSP only

Switch to virtual address Control register programming SET in PSR bn(44), it(36), rt(27), dt(17), ic(13)

Clear task priority register=cr.tpr

Clear interruption function state register-cr.ifs

Set legacy BIOS cs.base and ss.base

Set es,ds,fs,gs=0 with 4G limit Legacy BIOS module (eip)

Give control at xxxx:e05b to IA32 code

South

SAL-F Module

Table A-4. SAL-F POST Codes

Code Value

BSP, APs, Both

Meaning

Display

0x87BF

BSP

First check point. Check point in v6b00_83_ip2x. Update EBDA entry inside SST Create EFI memory descriptor Update SST checksum

South

0x87BE

BSP

Check point near v6b00_83_5 Search FIT for ACPI module (SAL_C_module_17) and get size, align, scratch buff size

South

0x07BE

BSP

Hang if ERROR

South

0x87BD

BSP

Load image by module type (sal_c_module_17). Use PELoader

South

0x07BD

BSP

Hang if not found. Get entry point, and GP value

South

0x87BC

BSP

Load image by module type (sal_c_module_17). Flush cache

South

0x07BC

BSP

Hang on ERROR. Build MP & ACPI table

South

0x87BB

BSP

Initialize memory manager (0x0) by call to SAL_C

South

0x07BB

BSP

Hang on ERROR

South

0x87BA

BSP

Feed system information (0x1) with call to SAL_C

South

0x07BA

BSP

Hang on ERROR

South

0x87B9

BSP

Initialize MP table v1.4 (0x2) with call to SAL_C

South

0x07B9

BSP

Hang on ERROR

South

0x87B8

BSP

Initialize IA32 ACPI v1.1 (0x3) with call to SAL_C

South

0x07B8

BSP

Hang on ERROR

South

0x87B7

BSP

Initialize IA64 ACPI v1.1 (0x4) with call to SAL_C

South

0x07B7

BSP

Hang on ERROR

South

0x87B6

BSP

Initialize IA32&IA64 ACPI v2.0 (0x5) with call to SAL_C

South

0x07B6

BSP

Hang on ERROR

South

0x87B5

BSP

Clear scratch memory (0xFFF) with call to SAL_C

South

0x07B5

BSP

Hang on ERROR

South

0x87B4

BSP

Search FIT for EFI module with call to PELoader. Get Size, align, and scratch buff size

South

0x07B4

BSP

Hang on ERROR. Get entry point, and GP value

South

0x87B3

BSP

Load image by module type (sal_c_module_17)

South

0x07B3

BSP

Hang on ERROR. Get entry point, and GP value

South

0x87B2

BSP

Flush cache with PAL call

South

0x07B2

BSP

Hang on ERROR

South

0x87B1

BSP

Build EFI input parameter table. Get EFI stack, bspstore etc. with EFI call

South

0x07B2

BSP

Hang on ERROR

South

0x87B0

BSP

Build EFI input parameter table. Get EFI stack, bspstore etc. with EFI call. Store EFI stack, bspstore etc. with EFI call. Call EFI and that should be end

South

0x07B0

BSP

Hang on ERROR if OK come back from EFI

South

IA32 Module

The IA32 POST codes all have the most significant bit (MSB) cleared by the convention established above. Also, the IA32 POST codes do not fall into the IA64 module definition above. The codes shown here are consistent with the 7.0 AMI core.

Table A-5. IA32 POST Codes

Code Value

Module

Display

0x00D0

Power on delay is starting. Next, the initialization code checksum is verified.

South

0x00D1

Initializing the DMA controller, performing the keyboard controller BAT test, starting memory refresh, and entering 4GB flat mode next.

South

0x00D3

Starting memory sizing next.

South

0x00D4

Returning to real mode. Executing any OEM patches and setting up the stack next.

South

0x00D5

Passing control to the uncompressed code in shadow RAM at E000 0000h. The initialization code is copied to segment 0 and control is transferred to segment 0.

South

0x00D6

Control is in segment 0. If the system BIOS checksum is bad, next goes to checkpoint code E0h. Otherwise, goes to checkpoint code D7h.

South

0x00D7

Passing control to the interface module next.

South

0x00D8

The main system BIOS runtime code will be decompressed next.

South

0x00D9

Passing control to the main system BIOS in shadow RAM next.

South

0x0003

Next, checking for a soft reset or a power on condition.

South

0x0005

The BIOS stack has been built. Next, disabling cache memory.

South

0x0006

Uncompressing the POST code next.

South

0x0008

The CMOS checksum calculation is done next.

South

0x000B

Next, performing any required initialization before the keyboard BAT command is issued.

South

0x000C

The keyboard controller input buffer is free. Next, issuing the BAT command to the keyboard controller.

South

0x000E

The keyboard controller BAT command result has been verified. Next, performing any necessary initialization after the keyboard controller BAT command test.

South

0x000F

The initialization after the keyboard controller BAT command test is done. The keyboard command byte is written next.

South

0x0010

The keyboard controller command byte is written. Next, issuing the Pin 23 and 24 blocking and unblocking commands.

South

0x0011

Check for INS key pressed. Get POST info.

South

0x0012

Disable DMA controllers 1 and 2 and interrupt controllers 1 and 2.

South

0x0013

The video display has been disabled. Next, initializing the chipset.

South

0x0014

The 8254 timer test begins next.

South

0x0019

The 8254 timer test is over. Starting the memory refresh test next.

South

0x001A

The memory refresh line is toggling. Checking the 15-second on/off time next.

South

0x0023

Reading the 8042 input-port and disabling the MEGAKEY Green PC feature next. Making the BIOS code segment writeable and performing any necessary configuration before initializing the interrupt vectors.

South

0x0024

The configuration required before interrupt vector initialization has completed. Interrupt vector initialization is about to begin.

South

0x0025

Interrupt vector initialization is done. Clearing the password if the POST DIAG switch is on.

South

0x0027

Any initialization before setting video mode is to be done next.

South

0x0028

Initialization before setting the video mode is complete. Configuring the monochrome mode and color mode settings next.

South

0x002A

Bus initialization system, static, output devices is to be done next, if present. Starting LAN redirection, displaying redirection console message.

South

Note that there are 15-bit postcodes in this area. These indicate Device Initialization Manager sub-codes

The convention for the DIM POST codes is as follows:
Port 80 = 0x2A
Port 81 = DIM Function number | DI number

South

0x002B

Passing control to the video ROM to perform any required configuration before the video ROM test.

South

0x002C

All necessary processing before passing control to the video ROM is done. Looking for the video ROM next and passing control to it.

South

0x002D

The video ROM has returned control to BIOS POST. Performing any required processing after the video ROM had control.

South

0x002E

Completed post-video ROM test processing. If the EGA/VGA controller is not found, performing the display memory read/write test next.

South

0x0037

The display mode is set. Displaying the power on message next.

South

0x0038

Initializing the bus input, IPL, and general devices next, if present.

South

0x0039

Late processor self test. Displaying bus initialization error messages.

South

0x003A

The new cursor position has been read and saved. Displaying the Hit F2 message.

South

0x0053

The memory size information and the CPU registers are saved.

South

0x0054

Shutdown was successful. Disabling the Gate A20 line, and parity next.

South

0x0057

The A20 address line, parity disabled. Adjusting the memory size depending on relocation and shadowing next.

South

0x0058

The memory size was adjusted for relocation and shadowing. Clearing the Hit F2 message.

South

0x0059

The Hit F2 message is cleared. Starting the DMA and interrupt controller test next.

South

0x0060

The DMA page register test passed. Performing the DMA Controller 1 base register test next.

South

0x0062

The DMA controller 1 base register test passed. Performing the DMA controller 2 base register test next.

South

0x0065

The DMA controller 2 base register test passed. Programming DMA controllers 1 and 2 next.

South

0x0066

Completed programming DMA controllers 1 and 2. Initializing the 8259 interrupt controller next.

South

0x007F

-

South

0x0080

Mouse initialization of PS/2 mouse to program the IRQ level to edge triggered or level triggered. The keyboard test has started. Clearing the output buffer and checking for stuck keys. Issuing the keyboard reset command next.

South

0x0082

The keyboard controller interface test completed. Write the command byte and initializing the circular buffer next.

South

0x0083

The command byte was written and global data initialization has completed. Checking for a locked key next.

South

0x0084

Locked key checking is over. Identify ATAPI devices.

South

0x0089

The programming after Setup has completed. Displaying the power on screen message next.

South

0x008B

Init boot devices. Check for and reset mouse.

South

0x008C

Npost adjustments to setup. Form E820 tables. Program SETUP-selected chipset and Sup-IO parameters.

South

0x008D

The Setup options are programmed. Resetting the hard disk controller.

South

0x008E

OEM patches executed. Decompress INT13 module and init ATA & ATAPI devices.

South

0x0093

Done with ATA & ATAPI init. Set RS-232 time out.

South

0x0095

Initializing the bus option ROMs from C800 next. SCSI opt ROM init.

South

0x0091

Configuring the hard disk drive controller. Initializing the CD ROM drive.

South

0x0092

-

South

0x0098

The adaptor ROM had control and has now returned control to BIOS POST. Performing any required processing after the option ROM returned control. Restoring INT10 vector.

South

0x0099

Configuring the timer data area and printer base address.

South

0x009B

Returned after setting the RS-232 base address. Performing any required initialization.

South

0x009E

Initialization. Checking the extended keyboard, keyboard ID, and Num Lock key next. Issuing the keyboard ID command.

South

0x00A2

Displaying any soft errors.

South

0x00A3

The soft error display has completed. Setting the keyboard typematic rate.

South

0x00A4

The keyboard typematic rate is set. Programming the memory wait states next.

South

0x00A5

Memory wait state programming is over. Clearing the screen.

South

0x00A7

Performing any initialization required before passing control to the adaptor ROM at E000 next.

South

0x00AE

Setting up DMI structures.

South

0x0020

Talking to BMC.

South

0x0022

Talking to BMC.

South

0x00AC

Uncompressing the DMI data and initializing DMI POST.

South

0x00AB

Building the multiprocessor table.

South

0x00AD

Prepare INT10 image. Update the necessary data in different modules.

South

0x00A8

Initialization before passing control to the adaptor ROM at E000h completed. Pass control to the adaptor ROM at E000h.

South

0x00A9

Returned from adaptor ROM at E000h control. Performing any initialization required after the E000 option ROM had control next.

South

0x00AA

Initialization after E000 option ROM control has completed. Displaying the system configuration.

South

0x00B1

Copying any runtime code to specific areas.

South

0x0000

Code copying to specific areas is done. Pass control to EFI.

South

Table A-6. SAL Runtime POST codes

Code Value

Module

Display

0xAFCD

IA32 Intercept Trap due to an unsupported IA32 instruction

South

0xAFE8

Normal SAL Machine Check Handling in Progress

South

0xAFE9

Could Not Correct MC Error, Halting CPU

South

0xAFEA

MCA successfully completed, passing control back to PAL (Resume)

South

0xAFEB

Calling OS MCA for Machine Check error handling

South

0xAFEC

Machine Check Handler Processing Rendezvous Request

South

0xAFED

OS request for SAL Clear Processor/Platform Error/State Log in progress

South

0xAFEE

SAL Platform OEM MCA Error Handler In Control

South

0xAFEF

OS request for SAL Get Processor/Platform Error/State Log in progress

South

0xAFF0

SAL INIT Handler is in control

South

0xAFF1

Passing Control to IA32 OS Init Handler

South

0xAFF2

Found valid OS_INIT Ep, Passing Control to EM OS Init Handler

South

0xAFF3

Is a MP platform MCA condition, calling SAL_RENDZ

South

0xAFF4

Not a MP Platform MCA Init condition

South

0xAFF5

EM OS with no Init Handler or IA32OS-BSP detected, Soft Rebooting

South

0xAFF6

No OS Init Handle Registered, Checking OS Type...

South

0xAFF8

SAL PMI Handler is in Control

South

0xAFFA

OEM SAL PMI Handler is in Control

South

0xAFFB

Getting Source of PMI Event

South

0xAFFC

Power Management PMI Handler is in Control

South

0xAFFD

Platform Error PMI Handler is in Control

South

0xAFFE

Platform Flash Management PMI Handler is in Control

South

0xAFFF

Platform Emulation PMI Handler is in Control

South

0xAF71

Recover Reliable Update - verifies the boot block checksum and corrects if possible

South


Recovery Port 80 Codes

Table A-7. Recovery POST Codes

Code Value

Module

Display

0x8EC0

Recovery Process Started

South

0x8EC1

Searching for Recovery Media

South

0x8EC2

Loading Recovery File

South

0x8EC3

Validating Recovery File

South

0x8EC4

Unlocking Flash Devices

South

0x8EC5

Erasing Flash Contents

South

0x8EC6

Programming Flash Contents

South

0x8EC7

Validating Flash Contents

South

0x8EC8

Recovery Process Complete

South


Error Codes – Video Display

The system BIOS displays POST error messages on the video screen. POST error codes are logged in the system event log.

The following table defines POST error codes and their associated messages. The BIOS prompts you to press a key in case of serious errors.

Some errors are displayed on the screen in red text. These are critical events that require user interaction and the BIOS POST pauses awaiting user input, prompting with a message requesting Press F1, F2, or ESC. This error code type is indicated in the table below as a Yes in the column heading Pause On Boot. This type of error causes the system to pause during system boot. Pausing for user interaction can be overridden in BIOS Setup.

Other error codes are displayed on the screen in yellow. These errors are noncritical and are displayed briefly, POST then continues. These errors are also logged to the SEL. This error code type is indicated in the table below as a No in the column heading Pause On Boot.

Table A-8. POST Error Messages and Codes

Error Code

Error Message

Attributes

Pause on Boot

103

CMOS Battery Failure

DFLT/RED_BLACK

Yes

104

CMOS Options not Set

DFLT/RED_BLACK

Yes

105

CMOS Checksum Failure

DFLT/RED_BLACK

Yes

109

Keyboard - Stuck key

DFLT/RED_BLACK

Yes

11B

Date/Time not set

DFLT/RED_BLACK

Yes

120

NVRAM cleared By jumper

DFLT/RED_BLACK

Yes

121

Password clear

WARN/YELLOW_BLACK

Yes

122

NVRAM cleared By Front panel

DFLT/RED_BLACK

Yes

140

PCI Error

DFLT/RED_BLACK

Yes

141

PCI Memory Allocation Error

DFLT/RED_BLACK

Yes

142

PCI IO Allocation Error

DFLT/RED_BLACK

Yes

143

PCI IRQ Allocation Error

DFLT/RED_BLACK

Yes

144

Shadow of PCI ROM Failed

DFLT/RED_BLACK

Yes

145

PCI ROM not found

DFLT/RED_BLACK

Yes

146

Insufficient Memory to Shadow PCI ROM

DFLT/RED_BLACK

Yes

8100

Processor 01 failed BIST

WARN/YELLOW_BLACK

Yes

8101

Processor 02 failed BIST

WARN/YELLOW_BLACK

Yes

8102

Processor 03 failed BIST

WARN/YELLOW_BLACK

Yes

8103

Processor 04 failed BIST

WARN/YELLOW_BLACK

Yes

8110

Processor 01 Internal error(IERR)

WARN/YELLOW_BLACK

Yes

8111

Processor 02 Internal error(IERR)

WARN/YELLOW_BLACK

Yes

8112

Processor 03 Internal error(IERR)

WARN/YELLOW_BLACK

Yes

8113

Processor 04 Internal error(IERR)

WARN/YELLOW_BLACK

Yes

8120

Processor 01: Thermal trip failure.

WARN/YELLOW_BLACK

Yes

8121

Processor 02: Thermal trip failure.

WARN/YELLOW_BLACK

Yes

8122

Processor 03: Thermal trip failure.

WARN/YELLOW_BLACK

Yes

8123

Processor 04: Thermal trip failure.

WARN/YELLOW_BLACK

Yes

8130

Processor 01: Disabled

WARN/YELLOW_BLACK

Yes

8131

Processor 02: Disabled

WARN/YELLOW_BLACK

Yes

8132

Processor 03: Disabled

WARN/YELLOW_BLACK

Yes

8133

Processor 04: Disabled

WARN/YELLOW_BLACK

Yes

8140

Processor 01: failed FRB level 3 timer

WARN/YELLOW_BLACK

Yes

8141

Processor 02: failed FRB level 3 timer

WARN/YELLOW_BLACK

Yes

8142

Processor 03: failed FRB level 3 timer

WARN/YELLOW_BLACK

Yes

8143

Processor 04: failed FRB level 3 timer

WARN/YELLOW_BLACK

Yes

8150

Processor 01: failed initialization on last boot

WARN/YELLOW_BLACK

Yes

8151

Processor 02: failed Initialization on last boot

WARN/YELLOW_BLACK

Yes

8152

Processor 03: failed initialization on last boot

WARN/YELLOW_BLACK

Yes

8153

Processor 04: failed initialization on last boot

WARN/YELLOW_BLACK

Yes

8192

L3 cache size mismatch

WARN/YELLOW_BLACK

No

8193

CPUID, Processor Steppings are different

WARN/YELLOW_BLACK

No

8196

Processor Models are Different

WARN/YELLOW_BLACK

No

8197

Processor speeds mismatched

DFLT/RED_BLACK

No

8210

Processor 1 Late Self Test Failed: Performance restricted

DFLT/RED_BLACK

Yes

8211

Processor 2 Late Self Test Failed: Performance restricted

DFLT/RED_BLACK

Yes

8212

Processor 3 Late Self Test Failed: Performance restricted

DFLT/RED_BLACK

Yes

8213

Processor 4 Late Self Test Failed: Performance restricted

DFLT/RED_BLACK

Yes

8220

Processor 1 Late Self Test Failed: Functionally restricted

DFLT/RED_BLACK

Yes

8221

Processor 2 Late Self Test Failed: Functionally restricted

DFLT/RED_BLACK

Yes

8222

Processor 3 Late Self Test Failed: Functionally restricted

DFLT/RED_BLACK

Yes

8223

Processor 4 Late Self Test Failed: Functionally restricted

DFLT/RED_BLACK

Yes

8230

Processor 1 Late Self Test Failed: Catastrophic failure

DFLT/RED_BLACK

Yes

8231

Processor 2 Late Self Test Failed: Catastrophic failure

DFLT/RED_BLACK

Yes

8232

Processor 3 Late Self Test Failed: Catastrophic failure

DFLT/RED_BLACK

Yes

8233

Processor 4 Late Self Test Failed: Catastrophic failure

DFLT/RED_BLACK

Yes

8300

Baseboard Management Controller failed to function

DFLT/RED_BLACK

Yes

8306

OS boot watchdog timer failure

DFLT/RED_BLACK

Yes

84F3

Baseboard Management Controller in Update Mode

DFLT/RED_BLACK

Yes

84FF

System Event Log Full

DFLT/RED_BLACK

Yes

8500

Multi-bit Error Detected Row1. Row mapped out.

WARN/YELLOW_BLACK

Yes

8501

Multi-bit Error Detected Row2. Row mapped out.

WARN/YELLOW_BLACK

Yes

8502

Multi-bit Error Detected Row3. Row mapped out.

WARN/YELLOW_BLACK

Yes

8503

Multi-bit Error Detected Row4. Row mapped out.

WARN/YELLOW_BLACK

Yes

8504

Persistent Single-bit Error Detected Row1. Row mapped out.

WARN/YELLOW_BLACK

Yes

8505

Persistent Single-bit Error Detected Row2. Row mapped out.

WARN/YELLOW_BLACK

Yes

8506

Persistent Single-bit Error Detected Row3. Row mapped out.

WARN/YELLOW_BLACK

Yes

8507

Persistent Single-bit Error Detected Row4. Row mapped out.

WARN/YELLOW_BLACK

Yes

8508

Memory Mismatch detected Row1. Row mapped out.

WARN/YELLOW_BLACK

Yes

8509

Memory Mismatch detected Row2. Row mapped out.

WARN/YELLOW_BLACK

Yes

850A

Memory Mismatch detected Row3. Row mapped out.

WARN/YELLOW_BLACK

Yes

850B

Memory Mismatch detected Row4. Row mapped out.

WARN/YELLOW_BLACK

Yes

850C

DIMM1, memory board 1 defective.

WARN/YELLOW_BLACK

Yes

850D

DIMM2, memory board 1 defective.

WARN/YELLOW_BLACK

Yes

850E

DIMM3, memory board 1 defective.

WARN/YELLOW_BLACK

Yes

850F

DIMM4, memory board 1 defective.

WARN/YELLOW_BLACK

Yes

8510

DIMM5, memory board 1 defective.

WARN/YELLOW_BLACK

Yes

8511

DIMM6, memory board 1 defective.

WARN/YELLOW_BLACK

Yes

8512

DIMM7, memory board 1 defective.

WARN/YELLOW_BLACK

Yes

8513

DIMM8, memory board 1 defective.

WARN/YELLOW_BLACK

Yes

8514

DIMM1, memory board 2 defective.

WARN/YELLOW_BLACK

Yes

8515

DIMM2, memory board 2 defective.

WARN/YELLOW_BLACK

Yes

8516

DIMM3, memory board 2 defective.

WARN/YELLOW_BLACK

Yes

8517

DIMM4, memory board 2 defective.

WARN/YELLOW_BLACK

Yes

8518

DIMM5, memory board 2 defective.

WARN/YELLOW_BLACK

Yes

8519

DIMM6, memory board 2 defective.

WARN/YELLOW_BLACK

Yes

851A

DIMM7, memory board 2 defective.

WARN/YELLOW_BLACK

Yes

851B

DIMM8, memory board 2 defective.

WARN/YELLOW_BLACK

Yes


Beep Codes

During POST, fatal problems can occur before video is enabled. These fatal errors are conveyed by encoded beeps, coupled with POST debug codes.

In order to extend the useful range of the beep codes, without the need to have dozens of codes, the beeps are classified, and the POST debug card makes the distinction within the class.

Table A-9 details the various beep codes supported by the system.

Table A-9. Error Beep Codes

Beeps

Error Message

Description

3

Memory failure

Memory test failure. See table below for additional error information.

4

System timer

System timer is not operational.

5

Processor failure

Processor failure detected.

7

Processor exception interrupt error

The processor generated an exception interrupt.

8

Display memory read/write error

The system video adapter is either missing or its memory is faulty. This is not a fatal error.

9

ROM Checksum error

System BIOS ROM checksum error.

11

Invalid BIOS

General BIOS ROM error.

Table A-10. POST Memory Beep Error Codes – Debug Port Encoding List

Beep Code

Debug port error code (lower byte of North I2C debug display)



Meanings



Detail

3

CF9Fh

No valid memory was found in the system.

This indicates that the memory test has found no valid memory in the system. The system will not boot. A SEL log entry will be made in this case.

3

CF64h

Mismatched DIMMs in a row, and no valid memory to boot.

This indicates that only a single row is populated, and that row contains mismatched DIMMs, preventing booting. A SEL log entry will be made in this case.


Recovery Beep Codes

Table A-11. Recovery Mode Beep Codes

Beeps

Description

1 short – medium tone

BIOS Flash Update Started

2 short – medium tone

BIOS Flash Update Complete

Repeating – low tone

BIOS Recovery Error Occurred


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