The power on self test (POST) is responsible for testing the integrity of
the processor's SDRAM. After testing SDRAM, POST will attempt to transfer control
to either the default bootrom image or an alternate image. POST can also download
binary images over the service port and write them to flash memory. This enables
POST to perform a minimal amount of emergency recovery from FLASH errors.
POST Boot
Behavior
ROM Init
Power-on
After applying power, the ERR LED will illuminate (Figure
1). At this time postInit code initializes
the processor's internal registers and subsystems, including the SDRAM controller.
The processor's internal RAM is used as a tiny-stack for this stage of POST.
Control is then passed to the Ipostmain
routine for the SDRAM memory tests.
Figure 1. ROM Init
Initial POST
Programmable Logic Device and Service Port Initialization
IpostMain starts by initializing the service-port
and the system programmable logic devices (PLDs). If successful, the ERR LED
will extinguish and the RDY LED will turn on (Figure 2).
Figure 2. Initial POST
POST will then display a firmware version banner on the service port.
== POST Version nnn ==
Simple Access Test
The simple access test verifies that the processor can perform basic writes
and reads to the SDRAM. This test is identified by the flash of the FC1 LED
(Figure 3).
Figure 3. Simple Access
Bitwalk Test
This test first walks a one-bit then a zero-bit through the base of each bank
of SDRAM. This test is identified by the flash of the FC2 LED (Figure
4).
Figure 4. Bitwalk Test
Memory Size
This test verifies that the apparent size of SDRAM meets the minimum and maximum
sizes specified for the product. This test is identified by the flash of the
FC2LED (Figure 5).
Figure 5. Memory Size
Pattern Test
This test writes and reads a series of diagnostic patterns to each memory location
in SDRAM. This test is identified by the repeated flash of the SCSI2 LED (Figure
6). This test can take several seconds to complete.
Figure 6. Pattern Test
Address Test
This test writes and reads address tags to memory to test for bad SDRAM address
lines. This test is identified by the flash of the SCSI3LED (Figure
7). POST then relocates itself to SDRAM and moves its stack from processor
internal RAM to SDRAM. Control is then transferred to the SDRAM-based secondary
POST.
Figure 7. Address Test
Secondary POST
This stage of POST attempts to locate and execute the intermediate loader
or "bootrom". If the operator presses the interrupt button <Ctrl><P>
then POST will enter into the service menu. See POST Service
Menu for details.
Identify and Execute Bootrom
POST will examine the FLASH memory primary bootrom locations to determine whether
or not it contains a viable bootrom. If the bootrom appears valid then POST
will transfer control to it. If the bootrom image is considered invalid then
POST will repeat the bootrom checks at the location of the secondary bootrom.
This step is indicated by the flash of the SCSI4 LED (Figure
8).
Figure 8. Identify and Execute
Start of Bootrom
When POST starts a bootrom image
it will display a line like:
Bootrom (*FFF00100)(2)
The number in the first parenthesis is the address of the bootrom's startup
code. The number in the second parenthesis is flag to the operating system to
determine what type of boot it has - warm or cold. Bootrom code will set the
ERR LED when it reconfigures the PLD (Figure 9).
Figure 9. Start of bootrom
POST Service
Menu
The POST service menu is enabled by using a slim tool (for example, an unfolded
paper clip) to depress the unlabeled button between the RST button and the PWR
LED.
Figure 10. NMI 1
The button may be depressed any time during the memory tests.
Figure 11. NMI 2
After completing the memory tests POST will display:
== POST Version nnn ==
== POST MENU ==
A - Cold boot from [A]lternate bootrom
B - Cold [B]oot from primary bootrom
R - [R]eceive new boot image from serial port
V - full [V]ersion information
A - Cold boot from [A]lternate
bootrom
This option causes POST to transfer
control to the alternate bootrom image at address 0xFFE00100 and to treat it
as a cold boot.
This option causes POST to transfer control to the default, or primary, bootrom
image at address 0xFFF00100 and to treat it as a cold boot. After loading a
new bootrom image, select this option to boot the SNC.
R - [R]eceive new boot image from
serial port
This starts the ZMODEM transfer
engine that transfers a single binary bootrom image file to POST using the service
port. It will not receive other kinds of binary image files. If the transfer
is successful then POST will program the image into the FLASH memory device.
While waiting for the file, POST will display:
**B000000023be50
At this point, the operator may transfer the bootrom file to POST using the
ZMODEM protocol. Refer to terminal emulator documentation for further details.
After the file is transferred, POST will display:
File transfer and update PASSED
ZMODEM Messages:
Writing to flash:MMMMMMMM-NNNN
If errors are encountered, POST
will display appropriate messages along with the line:
File transfer and update FAILED
V- full [V]ersion information
This command will cause POST to
display its version number, build date, the machine it was built on, and the
user who built it. The display will look like:
POST version 0402.02 Built Apr 4 2001, 15:24:06 on TANGLEFOOT
by jimu
Error Displays
POST will flash the ERR LED along with the LEDs associated with
any failed test. Refer to the LED assignments in the normal POST sequence. Error
messages may also be displayed on the service port.
